Dynamic Partial based Single Event Upset (SEU) Injection Platform on FPGA
نویسندگان
چکیده
منابع مشابه
Dynamic Partial based Single Event Upset (SEU) Injection Platform on FPGA
SRAM based FPGAs are attracting considerable interest especially in aerospace applications due to their high reconfigurability, low cost and availability. However, these devices are strongly susceptible to space radiation effects which are able to cause unwanted single event upsets (SEUs) in the configuration memory. In order to mitigate the SEU effects, various methods have been investigated i...
متن کاملSingle Event Upset (SEU) in SRAM
Radiation in space is potentially hazardous to microelectronic circuits and systems such as spacecraft electronics. Transient effects on circuits and systems from high energetic particles can interrupt electronics operation or crash the systems. This phenomenon is particularly serious in complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) since most of modern ICs are implem...
متن کاملFault Tolerance Implementation within SRAM Based FPGA Designs based upon Single Event Upset Occurrence Rates
1 ABSTRACT Emerging technology is enabling the design community to consistently expand the amount of functionality that can be implemented within Integrated Circuits (ICs). As the number of gates placed within an FPGA increases, the complexity of the design can grow exponentially. Consequently, the ability to create reliable circuits has become an incredibly difficult task. In order to ease the...
متن کاملFirst evaluation of the Single Event Upset ( SEU ) risk for electronics in the CMS experiment
SEU error rates in the CMS tracker environment have been approximated with Monte Carlo simulations. The estimated upset rates for a submicron technology are 8.3 10-7 upsets/(bit s) at 4.9cm and 1.1 10-8 upsets/(bit s) at 49cm from the beam line, respectively. Comparison of simulation data with experimental proton irradiation benchmarks points to a tenfold underestimate of the actual rate. All t...
متن کاملSingle Event Upset Mitigation Techniques for SRAM-based FPGAs
This paper discusses high level techniques for designing fault tolerant systems in SRAM-based FPGAs, without modification in the FPGA architecture. TMR has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications. However, TMR comes with high area and power dissipation penalties. The new technique proposed in this paper was specifically de...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2013
ISSN: 0975-8887
DOI: 10.5120/13227-0653